01
Introduction to VLSI Digital Design
Overview of Digital design methodology, Representations of Digital Design and
understanding of digital systems, logic gates, combinational and sequential logic. Review
HDL’s and RTL implementation of digital logic systems.
02
Semiconductor technologies and CMOS fundamentals
Introduction to semiconductor technologies, logic gates, Review CMOS basics, CMOS
digital design concepts. Understanding CMOS process parameters and characterization of
logic gates.
03
ASIC design flow and Design for Testability
Overview of ASIC/SOC design flow, Digital Design Concepts and Introduction to design faults that occur during chip design. Understanding stuck at faults, transition faults, coupling faults, pattern sensitive faults, and dynamic faults.
04
Introduction To Design For Testability
a) DFT fundamentals
b) Need for DFT in chip design
c) Understanding fabrication flows and challenges
d) ATPG basics
05
DFT Scan requirements
a) Observability and Controllability
b) DFT Scan logic design
c) DFT Design rules
d) Scan register vs normal registers
e) Scan chains & Scan pipelines
f) Scan Insertion techniques
g) Scan protocol design
06
Block level & SoC level DFT design
a) DFT flows and process steps
b) Defining DFT scan constraints
c) DFT synthesis and review scan protocols
d) DRC Checks (DFT Rule Checks)
e) DRC Error reporting and categories
f) Over view of block level & SoC level DFT scan design
07
DFT Scan Design
a) Scan Chain Architecture
b) Mux-D Scan Design
c) Clocked Scan Design
d) Level Sensitive Scan Design(LSSD)
e) Enhanced Scan Design
f) Low-Power Scan Design
08
Introduction Logic BIST
a) BIST Controllers
b) BIST Test Pattern Generators
c) Test pattern compaction
d) BIST Architectures
e) Test Per Scan BIST
f) Test Per Clock BIST
g) STUMPS based BIST Architecture
h) CBILBO BIST Architecture
i) Coverage Driven Logic BIST
j) Low Power BIST
09
DFT Scan Insertion
a) Scan Synthesis flows
b) DFT tools and setup for scan insertion
c) Scan Constraints and protocol definitions
d) Setting ATE configuration
e) Scan Specifications
f) Pre and Post Scan checks
g) Identifying Scan Chains and Estimating Test Coverages
h) Scan DRC(DFT rule checker) checks
i) Scan Chain optimization
10
DFT Scan Violations and Fixes
a) Scan Issues with various design scenarious
b) Gated clocks and clock muxes, Clock Generators
c) Controllability of Asynchronous logic, resets
d) Scan Design initialization sequence
e) Scan Capture problems due to clock skews
f) Scan buffers, Shift registers, tristate & bidirectional ports
g) Latch based designs and combinational loops
11
Advanced DFT Design concepts
a) Scan chain insertion with Clock mixing and no mixing
b) Mixing clock edges, clocking on both edges
c) Internal clock domains
d) Lockup latch
e) Custom Scan paths
f) Scan in/out port sharing techniques
12
DFT Scan compression techniques
a) DFT Scan compression with limited scan pins
b) Scan Serializer and Deserializer
c) Block level and Chip level compression techniques
d) External and Internal clock usage for serializer and Deserializer clocks
e) Adaptive scan techniques
13
DFT BIST Architecture
a) BIST Architecture
b) Logic BIST
c) Memory BIST
d) RAM BIST
e) ROM BIST
f) Memory models
g) Memory Faults
h) Stuck open and short faults
i) Coupling faults
j) Pattern sensitive faults
k) Read Disturb faults
l) Dynamic faults, recovery faults retention faults
m) March Tests
n) Word oriented march tests
o) Inter and Intra word tests
p) Word coupling faults tests
q) MISR
14
Test Pattern Generation using ATPG flows
a) Design Tools
b) ATPG tools and setup
c) ATE tools
d) STIL patterns( Defines Test protocols, Test pattern and Test timing )
e) Build Mode, DRC Mode and Test Mode
15
ATPG pattern generation concepts
a) ATPG pattern generation constraints
b) Analyzing DFT rule violations
c) ATPG coverage estimation
d) ATPG STIL pattern generation
e) Dynamic and Static Pattern compression techniques
f) Review results Detectable and undetectable faults
16
ATPG Fault modeling and simulations
a) Fault Simulation with functional patterns
b) Fault Grading for functional simulations
c) Design Verification setup with ATPG fault model simulations
d) Memory modeling for ATPG simulations
17
Final Project
Project on Block level and SoC level DFT insertion and ATPG generation with fault model simulations
To all VLSI aspiring minds, QuestVLSI technologies provides excellent ASIC DFT Design Course, trainers having very good experience teaching, It train's candidate with industry standard tools, thus makes candidate to meet industry requirement.
Suresh sunke
April 14, 2019