Advanced Verilog Concepts, Constant Functions, Enhanced Operators, Re-entrant tasks and Recursive Functions, FILE I/O, Common Compiler Directives, Enhanced condition compilation, Attributes, Enhanced Invocation Option Tests, New Timing Constraint Checks, Verilog Configurations, Verilog Generate, Verilog PLI, HVL Based verification.

Linting Tools, Simulators, Waveform Viewers, Source Debugging Tools, Code Coverage Tools, Functional/Assertion Coverage Tools

Functional Verification Process, Test Plan Development, TestBench Development, Testcase Development, Behavioral Models Development, BFM's Developments, Monitors Development, Checker Development, Functional group & Assert group Development using OVL & SVA, Module/Block/Chip Level Verification, Coverage driven Random Verification, Verification Metric Analysis (Code & Function coverage analysis)

Zero-Delay Gate-Level Verification, SDF-Annotated Gate-Level Verification, Timing Verification Process, Introduction to Formal Verification, Introduction Power-Aware Verification, Introduction to co-simulation verification, Introduction to AMS Verification, Introduction to Physical Verification.

Introduction to Scripting using Perl, Linux/Unix Utilities, FTP, Telnet, Version Management, Bug Tracking.

Language evolution, SV Design, SV Assertions, SV testbench, DPI, API

Data types, type checking, type cast, structure and union, Packages, Enhanced always, case/if... else, loop, flow, Operators, Arrays and its operators, SV scheduling semantics, DUT description1, Interface, Grouping signals, Modport, Clocking block, skews, Tasks, functions, Transaction Level Modeling (TLM)

OOP, cast, inheritance, polymorphism, parameterization, new constructor, Automatic, garbage collection, Virtual interface, task and function, automatic and static, void, extern, Argument pass by value/reference, Program construct, Final block, Enhanced Concurrency modeling, Threads – variants of fork .. join, Disable fork, terminate, Inter process communication, semaphore, mailboxes, queues

Need for random testing, Constraints in SVTB, Class constraint, Randomize success / fail, Inheritance, Randomize.with(), Distribution, Function calls in constraints, Array constraints, Pre / post randomize

Motivation, Introduction, Types of coverage, Functional coverage process, Covergroup, Coverpoint, Concept of binning, Cross Coverage, Sampling events.

Import & Export DPI, Context Based, DPI vs. VPI/PLI

Overview of different verification methodologies, Evolution of Verification methodologies, Migration of OVM to UVM, Introduction to UVM, Verification phasing, Reporting, Transactions, Test bench Configuration, TLM Basics, Events, Sequence, Sequencer and Driver, Virtual Sequences, Monitor & Subscriber, Agents, UVM Environment, Test bench classes, Callbacks, Coverage, Register layer

UVM Base Classes, Introduction to UVM core base classes, `include files and macros, Block diagram of DUT-testbench structure, UVM verification components, UVM components and objects, UVM transactions (passing OVM/UVM data & methods - dynamic class objects), UVM factory basics, Reporting methods & arguments, How to set OVM/UVM-reporting configurations, Reporting - file I/O

UVM components to build the testbench structure, UVM testbench structure (quasi-static class objects), UVM_component constructors, UVM components connected through ports & exports, Testbench driver (get-port configuration), Managing the virtual interface - config table - required dynamic casting, Testbench sequencer (get-export configuration), Testbench agent & environment, User-defined testbench package, UVM factory basics, Why is a factory used in UVM, What is needed to use the factory, Component and data lookup from the factory, Running without re-compilation, Tests can make substitutions without changing the testbench source code, Introduction to factory overrides, TLM ports & exports, TLM put, get and transport configurations, Transaction-level control flow, Transaction-level data flow, Transaction-level transaction type, Put configurations, Get configurations, Transport configurations

AHB Master/slave, AXI Master/Slave, AHB-I2C, AHB Uart, AHB DDR3/4 Memory controller, Ethernet/PCI/USB

Basics of analog circuit design concepts, Analog circuit design challenges and implementation strategies, Introduction to Analog layout concepts, Layout design rules and process

Introduction to fabrication techniques, Ionization and wafer technology, CMOS/BJT/MOSFET/FINFET IC fabrication steps, Fabrication techniques for Deep submicron technology

Understanding various mask layers, Layout requirements for each layers, Layout floor planning, BUMP/PAD/ESD/PIN planning

Creating libraries, adding and managing layout cell views, Creating config views for DRC/LVS checks, Layout editor tool commands and shortcuts, Commands for creating netlist from schematics and exporting to layout view, Layout spice simulation commands

Layout of basic CMOS gates, INV, AND, NAND, OR, NOR, Complex cell layout design

BJT, DIODE, Clamp cell designs, Resister, Capacitors, Inductors design, BiCMOS logic designs

Orientations, Multifingers/common Centriod/Quads, Distance/Gaps between layout layers, Overlaying and Adjacent layers, Same Area/Perimeter ratios, soft edge shapes

DRC/ERC/LVS soft checks, Electro migration checks and Removal techniques, IR Drop analysis, Antenna affect checks and Removal techniques, SI checks like crosstalk and EMI issues, ESD checks and ESD cell designs, Dish effects checks and removal, Well proximity checks

Analog Amaplifiers, comparators, filters circuits, Opamp sense amplifier designs, Differential Opamp Designs, Bandgap layout Designs, BUMP/ESD/Gaurd ring designs, Tap Cell Designs

SRAM cell design, Rows and Columns Decoders, Sense Amplifier design, Write/read control logic, Power supply design, Dual port RAM cell designs

1. PLL, LDO, ADC layouts. In 65nm, 32nm, 14nm
2. Assignments given for Lab practice

Overview of Digital design methodology, Representations of Digital Design and understanding of digital systems, logic gates, combinational and sequential logic. Review HDL’s and RTL implementation of digital logic systems.

Introduction to semiconductor technologies, logic gates, Review CMOS basics, CMOS digital design concepts. Understanding CMOS process parameters and characterization of logic gates.

Overview of ASIC/SOC design flow, Digital Design Concepts and Introduction to design faults that occur during chip design. Understanding stuck at faults, transition faults, coupling faults, pattern sensitive faults, and dynamic faults

a) DFT fundamentals
b) Need for DFT in chip design
c) Understanding fabrication flows and challenges
d) ATPG basics

a) Observability and Controllability
b) DFT Scan logic design
c) DFT Design rules
d) Scan register vs normal registers
e) Scan chains & Scan pipelines
f) Scan Insertion techniques
g) Scan protocol design

a) DFT flows and process steps
b) Defining DFT scan constraints DFT synthesis and review scan protocols
c) DRC Checks (DFT Rule Checks)
d) DRC Error reporting and categories
e) Over view of block level & SoC level DFT scan design

a) Scan Chain Architecture
b) Mux-D Scan Design
c) Clocked Scan Design
d) Level Sensitive Scan Design(LSSD)
e) Enhanced Scan Design
f) Low-Power Scan Design

a) BIST Controllers b) BIST Test Pattern Generators
c) Test pattern compaction
d) BIST Architectures
e) Test Per Scan BIST
f) Test Per Clock BIST
g) STUMPS based BIST Architecture
h) CBILBO BIST Architecture
i) Coverage Driven Logic BIST
j) Low Power BIST

a) Scan Synthesis flows
b) DFT tools and setup for scan insertion
c) Scan Constraints and protocol definitions
d) Setting ATE configuration
e) Scan Specifications
f) Pre and Post Scan checks
g) Identifying Scan Chains and Estimating Test Coverages
h) Scan DRC(DFT rule checker) checks
i) Scan Chain optimization

a) Scan Issues with various design scenarious
b) Gated clocks and clock muxes, Clock Generators
c) Controllability of Asynchronous logic, resets
d) Scan Design initialization sequence
e) Scan Capture problems due to clock skews Scan buffers, Shift registers, tristate & bidirectional ports
f) Latch based designs and combinational loops

a) Scan chain insertion with Clock mixing and no mixing
b) Mixing clock edges, clocking on both edges
c) Internal clock domains
d) Lockup latch
e) Custom Scan paths
f) Scan in/out port sharing techniques.

a) DFT Scan compression with limited scan pins
b) Scan Serializer and Deserializer
c) Block level and Chip level compression techniques
d) External and Internal clock usage for serializer and Deserializer clocks
e) Adaptive scan techniques

BIST Architecture, Logic BIST, Memory BIST, RAM BIST, ROM BIST, Memory models, Memory Faults, Stuck open and short faults, Coupling faults, Pattern sensitive faults, Read Disturb faults, Dynamic faults, recovery faults retention faults, March Tests, Word oriented march tests, Inter and Intra word tests, Word coupling faults tests, MISR

a) Design Tools
b) ATPG tools and setup
c) ATE tools
d) STIL patterns( Defines Test protocols, Test pattern and Test timing )
e) Build Mode, DRC Mode and Test Mode

a) ATPG pattern generation constraints
b) Analyzing DFT rule violations
c) ATPG coverage estimation
d) ATPG STIL pattern generation
e) Dynamic and Static Pattern compression techniques
f) Review results Detectable and undetectable faults

a) Fault Simulation with functional patterns
b) Fault Grading for functional simulations
c) Design Verification setup with ATPG fault model simulations
d) Memory modeling for ATPG simulations

Project on Block level and SoC level DFT insertion and ATPG generation with fault model simulations