Advanced Verilog Concepts, Constant Functions, Enhanced Operators, Re-entrant tasks and Recursive Functions, FILE I/O, Common Compiler Directives, Enhanced condition compilation, Attributes, Enhanced Invocation Option Tests, New Timing Constraint Checks, Verilog Configurations, Verilog Generate, Verilog PLI, HVL Based verification.

Linting Tools, Simulators, Waveform Viewers, Source Debugging Tools, Code Coverage Tools, Functional/Assertion Coverage Tools

Functional Verification Process, Test Plan Development, TestBench Development, Testcase Development, Behavioral Models Development, BFM's Developments, Monitors Development, Checker Development, Functional group & Assert group Development using OVL & SVA, Module/Block/Chip Level Verification, Coverage driven Random Verification, Verification Metric Analysis (Code & Function coverage analysis)

Zero-Delay Gate-Level Verification, SDF-Annotated Gate-Level Verification, Timing Verification Process, Introduction to Formal Verification, Introduction Power-Aware Verification, Introduction to co-simulation verification, Introduction to AMS Verification, Introduction to Physical Verification.

Introduction to Scripting using Perl, Linux/Unix Utilities, FTP, Telnet, Version Management, Bug Tracking.

Language evolution, SV Design, SV Assertions, SV testbench, DPI, API

Data types, type checking, type cast, structure and union, Packages, Enhanced always, case/if... else, loop, flow, Operators, Arrays and its operators, SV scheduling semantics, DUT description1, Interface, Grouping signals, Modport, Clocking block, skews, Tasks, functions, Transaction Level Modeling (TLM)

OOP, cast, inheritance, polymorphism, parameterization, new constructor, Automatic, garbage collection, Virtual interface, task and function, automatic and static, void, extern, Argument pass by value/reference, Program construct, Final block, Enhanced Concurrency modeling, Threads – variants of fork .. join, Disable fork, terminate, Inter process communication, semaphore, mailboxes, queues

Need for random testing, Constraints in SVTB, Class constraint, Randomize success / fail, Inheritance, Randomize.with(), Distribution, Function calls in constraints, Array constraints, Pre / post randomize

Motivation, Introduction, Types of coverage, Functional coverage process, Covergroup, Coverpoint, Concept of binning, Cross Coverage, Sampling events.

Import & Export DPI, Context Based, DPI vs. VPI/PLI

Overview of different verification methodologies, Evolution of Verification methodologies, Migration of OVM to UVM, Introduction to UVM, Verification phasing, Reporting, Transactions, Test bench Configuration, TLM Basics, Events, Sequence, Sequencer and Driver, Virtual Sequences, Monitor & Subscriber, Agents, UVM Environment, Test bench classes, Callbacks, Coverage, Register layer

UVM Base Classes, Introduction to UVM core base classes, `include files and macros, Block diagram of DUT-testbench structure, UVM verification components, UVM components and objects, UVM transactions (passing OVM/UVM data & methods - dynamic class objects), UVM factory basics, Reporting methods & arguments, How to set OVM/UVM-reporting configurations, Reporting - file I/O

UVM components to build the testbench structure, UVM testbench structure (quasi-static class objects), UVM_component constructors, UVM components connected through ports & exports, Testbench driver (get-port configuration), Managing the virtual interface - config table - required dynamic casting, Testbench sequencer (get-export configuration), Testbench agent & environment, User-defined testbench package, UVM factory basics, Why is a factory used in UVM, What is needed to use the factory, Component and data lookup from the factory, Running without re-compilation, Tests can make substitutions without changing the testbench source code, Introduction to factory overrides, TLM ports & exports, TLM put, get and transport configurations, Transaction-level control flow, Transaction-level data flow, Transaction-level transaction type, Put configurations, Get configurations, Transport configurations

AHB Master/slave, AXI Master/Slave, AHB-I2C, AHB Uart, AHB DDR3/4 Memory controller, Ethernet/PCI/USB