Overview of Digital design methodology, Representations of Digital Design and understanding of digital systems, logic gates, combinational and sequential logic. Review HDL’s and RTL implementation of digital logic systems.

Introduction to semiconductor technologies, logic gates, Review CMOS basics, CMOS digital design concepts. Understanding CMOS process parameters and characterization of logic gates.

Overview of ASIC/SOC design flow, Digital Design Concepts and Physical Design flow setup. Review of ASIC fundamentals & fabrication methodologies.

a) Introduction to digital design
b) Number representation, complements and Boolean logic
c) Basic logic gates and logic functions
d) Optimization techniques for logic functions
e) Design of combinational circuits.
f) Implementation and analysis of combinational circuits like, adders, comparator, multiplier etc.
g) Design of synchronous sequential circuits.
h) Implementation and analysis of sequential circuits Flip-Flops, registers, counters, and simple processor
i) Design of Asynchronous Sequential Circuits
j) Design of Finite State Machines (FSM)
k) Discussion - Special circuits like LFSR, FIFO, barrel shifter etc.
l) Case study – PROTOCOLS LIKE AHB, APB, PCI, UART etc

a) Introduction to Verilog HDL.
b) Gate-Level modeling.
c) Dataflow modeling.
d) Operators.
e) Data types.
f) Modeling timing and delays.
g) Behavioral modeling.
h) Parameters, tasks and functions.
i) Compiler directives.
j) System tasks.
k) File input/output.
l) Switch-level modeling.
m) User Defined Primitives.
n) Design examples – FSM, ALU, RAM, ROM, UART, Traffic light signal.

a) Introduction to SystemVerilog HDL.
b) Systemverilog Design enhancements.
c) New data types & user Defined data types
d) Interfaces
e) New combinational logic constructs
f) Sequential logic design with always_ff
g) Advanced FSM Design techniques using SV
h) Parameters, tasks and functions.
i) Enhanced module definations and instance mappings
j) Multidimensional packed array declarations

a) Introduction to ASIC's and ASIC flows
b) Insight into various ASIC design Architecture
c) Writing RTL for ASIC design flow
d) ASIC Design Flow using Synopsys and cadence Tools
e) Using special digital modules in ASIC design
f) Static RAM and Dynamic RAM
g) Clock and Reset managements, power sequencing
h) Clock gating and low power designs
i) Dedicated arithmetic functions

a) Simulation and synthesis issues.
b) RTL design strategies.
c) Static timing analysis

a) Introduction to STA
b) Comparison with DTA
c) Timing Path and Constraints
d) Different types of clocks
e) Clock domain and Variations
f) Clock Distribution Networks
g) How to fix timing failure
h) Introductions to timing static and dynamic hazards,i) Path delay, Gate delay, Metastability states.
j) Sequential timing delays like set-up time, hold time,
k) Maximum frequency, violations, slew, slack.
l) Delay analysis
m) Sequential logic pad to set up,
n) pad to pad,
o) clk to next Reg,
p) Reg to o/p and
q) Reg to Reg. violations wrt sequential circuit.

Introduction to RTL Lint, Lint rules & definations, EDA tools used. Linting checks and report generation, Probable simulation errors, matching gate level simulations with RTL simulations, RTL Coding guidelines, FSM state reachability and coding issues, connectivity checks for clocks, resets, and tri-state driven signals Module partitioning, Tool flow issues in the upcoming design cycle stages, Possible synthesis issues. (eg unintended latches or combo loops) Clocks and reset definitions.

Overview of CDC(Clock Domain Crossing), Introduction to CDC designs, understanding metastability, multi clock vlsi design requirements, differences between synchronous and asynchronous designs, types of clocks in multi clock domain designs, CDC synchronization techniques across multi clock designs, EDA tools for CDC checks, report generations, CDC rules definations and error & warnings classifications, fixing CDC issues and preparing for RTL releases.

Low power Design techniques, clock gating, muti power domain designs, multi Vt designs, UPF based power intent design, RTL Power aware designs, low power multi voltage design technques, isolation technqies, retention logic, level shifter requirements. low power design quality checks and report generations.

1. USB, PCIe, High speed serial interfaces, Advanced bus protocols like AHB, AXI interfaces
2. Memory controllers and DMA controller designs